In a programmable logic device (PLD), a logic circuit is formed using adequate-scale programmable logic elements (PLE), and the functions of the PLEs and connection between the PLEs can be changed after manufacture. Specifically, the PLD includes at least a plurality of PLEs and a routing resource for controlling connection between the PLEs.
The internal circuit structure of the programmable logic device can be changed by a user after manufacture. The PLE is the minimum unit of a logic resource included in a combinational circuit, a sequential circuit, or the like.
There are a variety of PLE structures proposed by PLD vendors. A look-up table (LUT)-type PLE including an LUT that can function as a variety of logic gates with a simple circuit structure and a flip-flop required to achieve the function of a sequential circuit is advantageous over a product-term type PLE that achieves a desired logic gate with a combination of an AND circuit and an OR circuit in an increase in PLD area and comes on the market.
An LUT-type PLE often includes a multiplexer for offering an option for a signal path in addition to an LUT and a flip-flop. By providing the multiplexer in the PLE, configuration data can control not only PLE internal connection, such as selection of signals input to the flip-flop or selection of signals output from the PLE, but also direct connection between the PLEs without a routing resource switch. Thus, the use of the multiplexer can reduce the number of PLEs and achieve a variety of circuit structures in the PLD.
Patent Document 1 discloses an FPGA including a plurality of multiplexers in a logic module.
Patent Document 1: Japanese Published Patent Application No. 08-330943